1. Field of the Invention
The present invention relates to integrated circuit (IC) devices, and in particular to a lateral double diffused metal-oxide-semiconductor (LDMOS) device and a method for fabricating the same.
2. Description of the Related Art
Recently, due to the rapid development of communication devices such as mobile communication devices and personal communication devices, wireless communication products such as mobile phones and base stations have been developed greatly. In wireless communication products, high-voltage elements of lateral double diffused metal-oxide-semiconductor (LDMOS) devices are often used as radio frequency (900 MHz-2.4 GHz) related elements therein.
LDMOS devices not only have a higher operation frequency, but they are also capable of sustaining a higher breakdown voltage, thereby having a high output power so that they can be used as power amplifiers in wireless communication products. In addition, due to the fact that LDMOS devices can be formed by conventional CMOS fabrications, LDMOS devices can be fabricated from a silicon substrate which is relatively cost-effective and employs mature fabrication techniques.
In FIG. 1, a schematic cross section showing a conventional N-type lateral double diffused metal-oxide-semiconductor (LDMOS) device applicable in a radio frequency (RF) circuit element is illustrated. As shown in FIG. 1, the N-type LDMOS device mainly comprises a P+ type semiconductor substrate 100, a P− type epitaxial semiconductor layer 102 formed over the P+ type semiconductor substrate 100, and a gate structure G formed over a portion of the P− type epitaxial semiconductor layer 102. A P− type doped region 104 is disposed in the P− type epitaxial semiconductor layer 102 under the gate structure G and a portion of the P− type epitaxial semiconductor layer 102 under the left side of the gate structure G, and a N− type drift region 106 is disposed in a portion of the P− type epitaxial semiconductor layer 102 under the right side of the gate structure G. A P+ type doped region 130 and a N+ type doped region 110 are disposed in a portion of the P type doped region 104, and the P+ doped region 130 partially contacts a portion of the N+ type doped region 110, thereby functioning as a contact region (e.g. P+ type doped region 130) and a source region (e.g. N+ type doped region 110) of the N type LDMOS device, respectively, and another N+ type doped region 108 is disposed in a portion of the P− type epitaxial semiconductor layer 102 at the right side of the N− type drift region 106 to function as a drain region of the N type LDMOS device. In addition, an insulating layer 112 is formed over the gate structure G, covering sidewalls and a top surface of the gate structure G and partially covering the N+ type doped regions 108 and 110 adjacent to the gate structure G. Moreover, the N type LDMOS further comprises a P+ type doped region substantially disposed in a portion of the P− type epitaxial semiconductor layer 102 under the N+ type doped region 110 and the P− type doped region 104 under the N+ type doped region 110. The P+ type doped region 120 physically connects the P− type doped region 104 with the P+ type semiconductor substrate 100.
During operation of the N type LDMOS device shown in FIG. 1, due to the formation of the P+ type doped region 120, currents (not shown) from the drain side (e.g. N+ type doped region 108) laterally flow through a channel (not shown) underlying the gate structure G towards a source side (e.g. N+ type doped region 110), and are then guided by the P− type doped region 104 and the P+ type doped region 120, thereby arriving the P+ type semiconductor substrate 100, such that problems such as inductor coupling and cross-talk between adjacent circuit elements can be avoided. However, formation of the P+ type doped region 120 needs to perform ion implantations of high doping concentrations and high doping energies and thermal diffusion processes with a relatively high temperature above about 900° C., and a predetermined distance D1 is kept between the gate structure G and the N+ type doped region 110 at the left side of the gate structure G to ensure good performance of the N type LDMOS device. Therefore, formation of the P+ type doped region 120 and the predetermined distance D1 kept between the gate structure G and the N+ type doped region 110 increase the on-state resistance (Ron) of the N type LDMOS device and a dimension of the N type LDMOS device, which is unfavorable for further reduction of both the fabrication cost and the dimensions of the N type LDMOS device.